register transfer simulation

英 [ˈredʒɪstə(r) trænsˈfɜː(r) ˌsɪmjuˈleɪʃn]

美 [ˈredʒɪstər trænsˈfɜːr ˌsɪmjuˈleɪʃn]

网络寄存器传送模拟

In IC design, it is a common method to set up behavior models for target systems by RTL ( Register Transfer Level) Verilog codes. People can find the potential logic bugs and primarily evaluate the performance of target systems by deploying software simulation for RTL codes.
在IC设计中，使用Verilog编写寄存器级描述（RTL）对目标系统建立行为级模型后，对RTL进行大量的软件仿真不仅可以及早发现潜在的逻辑错误，而且能够对目标系统的性能进行初步评估。
Finally, the architecture is described by Verilog HDL in register transfer level ( RTL). The synthesis, simulation and on-line debugging of this design are implemented with the assistance of EDA tools. And the result of simulation and synthesis is given out.
最后，采用Verilog硬件描述语言对整个结构进行寄存器传输级描述，用EDA工具完成了整个设计的仿真和综合，给出了仿真和综合的结果。
Register transfer level code verification is the most important factor in the design, therefore, two ways are analyzed in this thesis: logic function simulation and prototype verification.
寄存器传输级代码的验证是保证芯片功能正确的最关键因素，为此，本文讨论了逻辑功能仿真验证和原型验证这两种方法。